An optimally self-biased threshold-voltage extractor [MOSFET circuit parametric testing]

A novel threshold-voltage extractor architecture is presented. A differential-difference transconductor (DDT) loop automatically biases the device-under-test in continuous time around the inflection point of the I/sub D/ versus V/sub GS/ characteristics. Another DDT operates as an arithmetic processor to precisely implement multiplication by two and subtraction as needed for extrapolation. The extraction procedure thus complies entirely with all steps of the manual saturation method. With appropriate modifications, the architecture can also serve as an extractor implementing the linear method. The proposed architecture is applicable to both PMOS and NMOS on the same chip, and generates the value of V/sub T/ as a voltage with respect to the appropriate rail. It has been fabricated on silicon, and its accuracy has been experimentally verified by comparing automatically and manually extracted parameter values.