RSFQ random logic gate density scaling for the next-generation Josephson junction technology

Post-layout automatic analysis of Flux-1 microprocessor, a representative random logic RSFQ chip of more than 5000 gate complexity, allowed us to extract important layout parameters such as gate density, Josephson junction density and gate/wiring/unused area ratios. A scaling model is presented to predict the area required to layout a given number of random logic gates. When applied to Flux-1 chip itself, which occupies 88.6 mm/sup 2/ in the current TRWs 4 kA/cm/sup 2/ J110D technology, this model predicts that it can be shrunk by almost a factor of two in area to 49 mm/sup 2/ if moved to a nextgeneration J110E technology with 8 kA/cm/sup 2/ junctions. This information enables us to confidently floorplan random logic chips to be implemented in future advanced JJ technologies. It can also provide directions for JJ technology improvements leading to the maximum positive impact on RSFQ chip density.