Design issues for interconnects in densely packaged RSFQ structures

The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.