Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations

Process, device, and mixed-mode (device/circuit) simulation-based approach is presented for 0.1-(mu)m gate length CMOS technology optimization and sensitivity analysis. The disposable spacer-based 0.1-(mu)m NMOS and PMOS transistors with excellent short channel characteristics are designed using process and device simulations. The implant-dose sensitivity of the device parameters around the nominal value are estimated. The halo implant and super steep retrograde channel implant dose fluctuations are found to have a profound effect on device characteristics. It is shown that the mixed-mode device/circuit simulation can be used as an excellent tool to connect the circuit delay sensitivity to underlying process parameters. The simulation results demonstrate that the relation between circuit and process parameters is highly nonlinear for the deep submicron technology.