Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs

Programmable devices containing lookup tables (LUTs) and programmable logic arrays (PLAs) provide a heterogeneous target platform for user designs. Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource. In this paper, an automated technology mapping tool, hybridmap , is presented that identifies design logic partitions as suitable for either LUT or PLA implementation. A breadth-first search-based subgraph extraction and evaluation heuristic is integrated with product term (Pterm) count, area, and delay estimators to guide the technology mapping process. Hybridmap can be adapted to target a variety of PLA architectures and can accommodate user-provided timing constraints. It is shown that when timing constrained, hybridmap reduces LUT consumption for Apex20KE devices by 8% and when unconstrained by 14% by migrating logic from LUTs to Pterm structures. Hybridmap is shown to outperform previous mapping approaches for Apex20KE-type devices by up to 22%.