Timing optimization on routed designs with incremental placement and routing characterization

Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 (mu)m. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental results show that this algorithm provides better result after detail routing is completed.