Low-offset CMOS OEIC for optical storage systems

A low-area CMOS optoelectronic integrated circuit (OEIC) for optical storage (OS) systems containing photodiodes and transimpedance amplifiers with a low offset voltage is presented. The photodiodes and the amplifiers are monolithically integrated in a 0.6 (mu)m CMOS process. A replica transimpedance amplifier and a low-offset operational amplifier are implemented for offset reduction. A -3 dB frequency of 147 MHz and a sensitivity of 24 mV/(mu)W at 670 nm were measured, as well as an offset voltage deviation of 4 mV. The OS test OEIC containing four independent optical receivers occupies a chip area of only 0.52 mm/sup 2/. with this performance, an innovative low-cost CMOS OEIC is suggested being a true alternative to currently used BiCMOS OEICs.