Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-(kappa) gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-(kappa) dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.