Proposal of a multi-layer channel MOSFET: the application of selective etching for Si/SiGe stacked layers

A multi-layer channel MOSFET (ML-MOSFET) and its fabrication process were proposed for future CMOS application. ML-MOSFET has multi-Si channel layers stacked vertically, so that the drain current per 1 mm gate width on wafer is expected to increase with the number of channel layers compared to conventional double-gate MOSFET. Ion ¼ 3:9 mA/mm was obtained for ML-MOSFET with three Si channel layers (Lg: 10 nm, TSi: 2.5 nm) by the device simulation. Fabrication process of multilayer channel using selective etching for SiGe/Si stacked layers was also investigated. # 2003 Published by Elsevier B.V.