FPGA Implementation of Power and Area Efficient Compressed Sensing for Multi-Channel ECG Compression

This paper presents the design of a low-power and area efficient hardware engine for multi-channel compression of electrocardiogram (ECG) signals. Compressed sensing (CS) is particularly well suited for low-power implementations because it can dramatically reduce circuit complexity for compression operations. We also present a CS architecture which allows power gating. Another feature of the proposed architecture is that it is suitable for multi-channel systems. The design is implemented in a certain family of FGPAs which are suited for low-power applications. Our measurement results show an effective reduction of power consumption between 20 to 40 percent at different operating frequencies using power gating technique. The power consumption of a 4-channel system and an 8-channel system is increased only by 7.1% and 11.2% respectively, compared to the single-channel system. The area of the 4-channel system and the 8-channel system compared to the single-channel system is increased only by a factor of 2.3 and 5.4, respectively