Value-Aware Low-Power Register File Architecture

In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, ”Value-Aware Partitioned Register File (VAP-RF)”, employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrowvalue registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure.