Two Phase Nonoverlapping Clocked All-N-Logic in Subthreshold Region with 49fJ Power Delay Product

This paper represents a new structure of ANL logic, named TPSANL to achieve ultra low power with no glitches in the subthreshold region. Since different ANL logics suffer from output glitches due to race problem, our proposed TPSANL logic by using two phase nonoverlapping clocks eliminates output glitches and reduces the glitch power. The noninverting/inverting pipelined system in ANL logics causes a voltage drop on NMOS transistors in inverting blocks. Therefore, these logics cannot operate in subthreshold regions. TPSANL uses high speed noninverting blocks in all pipeline stages. So, it can operate in subthreshold region. One 4-bit CLA adder with TPSANL logic in the subthreshold region operates in 14.5MHz frequency with 157nW power consumption and 49fJ power-delay-product.