An Improvement of Reversible Fault Tolerant Adder/Subtractor Circuits

An Improvement of Reversible Fault Tolerant Adder/Subtractor Circuits

This paper present a Novel reversible Fault Tolerant gate and employed to implement one bit reversible Fault Tolerant full Add/Sub. The presented 1-bit full Add/Sub is implemented using VHDL and compared to previously presented designs in the literature. The results show that the presented design is more efficient in terms of number of DC inputs/outputs, delay and quantum cost. Two reversible Fault Tolerant four-bit parallel Add/Sub and carry skip Add/Sub are also designed applying the presented scheme and compared to the former designs