Design of A New Low-Power High-Speed CMOS Full Adder Cell

Design of A New Low-Power High-Speed CMOS Full Adder Cell

Full adder cell is one of the most fundamental building blocks in many digital circuits such as binary adders and regular multipliers. In this paper, a novel low-power highspeed 20-T full adder is presented which provides full-swing outputs and can work reliably even at low voltages. We first propose a new logic block diagram for full adder circuit and then using two main modules, i.e. low-power XOR-XNOR cell and transmission-gate (TG) based 2-to-1 multiplexers, implement our new design in transistor level. Our new design and some previously reported full adders are optimized with the same sizing algorithm at TSMC-0.18μm CMOS technology. Simulation results using HSPICE simulator shows that our proposed circuit offers significant enhancement in terms of power consumption and power-delay product (PDP) in comparison with the existing counterpart circuits.