• DocumentCode
    1001611
  • Title

    An SEU-hardened CMOS data latch design

  • Author

    Rockett, Leonard R., Jr.

  • Author_Institution
    IBM Corp., Manassas, VA, USA
  • Volume
    35
  • Issue
    6
  • fYear
    1988
  • fDate
    12/1/1988 12:00:00 AM
  • Firstpage
    1682
  • Lastpage
    1687
  • Abstract
    A single-event-upset hardened CMOS data latch design is described. The hardness is achieved by virtue of the design; thus no fabrication process or design ground-rule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests have provided hardness verification
  • Keywords
    CMOS integrated circuits; combinatorial circuits; integrated logic circuits; radiation hardening (electronics); CMOS data latch design; hardness verification; performance; single-event-upset hardened; CMOS logic circuits; Circuit simulation; Circuit testing; Clocks; Cyclotrons; Fabrication; Latches; Logic design; Process design; Single event upset;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.25522
  • Filename
    25522
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1001611