A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC

A burst-mode clock and data recovery circuit (CDR) for 10 G-EPON systems is described. We propose a new architecture with a single gated voltage-controlled oscillator (GVCO), a digital frequency detector, and a ΔΣ digital-to-analog converter (DAC). The single GVCO and detector reduce frequency error to less than 2 MHz. The ΔΣ DAC eliminates external devices. Moreover, the simulation results show the DAC is more tolerant to process, voltage, and temperature (PVT) variations than a conventional charge pump. We fabricated a test CDR with this architecture using the 0.25 μm SiGe BiCMOS process. The measurement results show root-mean-square (rms) and total jitter of the recovered data of 2.4 and 14.7 ps, respectively, instantaneous locking in 1 bit, tolerance to a 160-bit sequence without transition in the data, and jitter tolerance of over 0.27 UIpp.