A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique

Author

Nguyen, Khiem ; Bandyopadhyay, Abhishek ; Adams, Bob ; Sweetland, Karl ; Baginski, Paul

Author_Institution

Analog Devices, Wilmington, MA

Volume

43

Issue

12

fYear

2008

Firstpage

2592

Lastpage

2600

Abstract

A low power audio oversampling SigmaDelta digital-to-analog converter (DAC) with a three-level (+1, 0,-1) dynamic-element-matching (DEM) technique and an inter-symbol interference-free (ISI) output stage is presented. Solutions for design challenges such as ISI, clock jitter sensitivity, and out-of-band noise are presented. The converter is fabricated in a 0.18 mum CMOS process, occupies 0.55 mm², achieves 108 dB dynamic range, -98 dB THD + N while consumes a total of 1.1 mW per channel at 1.8 V supply.

Keywords

CMOS integrated circuits; digital-analogue conversion; jitter; SNR; clock jitter sensitivity; dynamic element matching; inter symbol interference free output stage; noise figure 108 dB; out-of-band noise; oversampling audio DAC; power 1.1 mW; three level DEM technique; voltage 1.8 V; CMOS process; Circuits; Clocks; Degradation; Digital-analog conversion; Dynamic range; Energy consumption; Intersymbol interference; Jitter; Signal to noise ratio; DAC; low power; oversampling; portable audio; sigma-delta;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.2006314

Filename

4684641