An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

Author

Liang, Chuan-Kang ; Yang, Rong-Jyi ; Liu, Shen-Iuan

Author_Institution

Nat. Taiwan Univ., Taipei

Volume

55

Issue

1

fYear

2008

Firstpage

361

Lastpage

369

Abstract

An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0.216 mm². The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 ~ 200 MHz and 60 ~ 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.

Keywords

CMOS digital integrated circuits; clocks; delay lock loops; frequency multipliers; frequency synthesizers; jitter; programmable circuits; CMOS fabrication process; all-digital delay-locked loop; all-digital fast-locking programmable DLL; clock generator; clock multiplication ratio; frequency 4 MHz to 200 MHz; frequency 60 MHz to 450 MHz; frequency synthesizer; minimal delay constraint; short locking time; size 0.35 mum; voltage 3.3 V; All-digital DLL; All-digital delay-locked loop (DLL); clock generator; clock multiplier; fast-locking; frequency synthesizer;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2007.913612

Filename

4400043