New proposal for a high-speed high-resolution analogue/digital convertor with reduced component count

A new analogue/digital convertor (ADC) architecture is proposed which is well suited to monolithic integration of high-speed high-resolution ADC systems. The new architecture uses a two-stage parallel-serial feedforward structure but replaces the conventional interstage digital/analogue convertor (DAC) with a distributed error amplifier. Circuit simulations predict an 8.4 ns cycle time (excluding sample-hold time requirements) for a 12-bit ADC integrated in an advanced 1 ¿m silicon bipolar technology.