• DocumentCode
    1006898
  • Title

    Latched domino CMOS logic

  • Author

    Pretorius, J.A. ; Shubat, A.S. ; Salama, C.A.T.

  • Author_Institution
    University of Toronto, Department of Electrical Engineering, Toronto, Canada
  • Volume
    21
  • Issue
    7
  • fYear
    1985
  • Firstpage
    263
  • Lastpage
    264
  • Abstract
    A new gate configuration: the latched domino (Idomino) CMOS gate is described in the letter. It can be used to alleviate the inversion problem inherent in domino CMOS logic. It retains the speed advantages of domino logic while improving logic flexibility and reducing area. The gate is compatible with standard domino logic.
  • Keywords
    CMOS integrated circuits; integrated logic circuits; logic gates; area reduction; inversion problem; latched domino CMOS logic; logic flexibility; logic gate;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19850187
  • Filename
    4251009
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1006898