Rip-up, reroute strategy accelerates routing process

This article describes the extension of an already existing routing system and explores the feasibility of combining this with a field-programmable gate array (FPGA)-based maze routing accelerator to speed up the routing process. The routing system makes use of a rip-up and reroute strategy and utilizes an evolution algorithm to make routing decisions. The FPGA hardware accelerator speeds up the process of routing individual nets. The routing processes may be significantly shortened by using the software to determine when nets are to be ripped up and rerouted and the hardware accelerator to perform individual routes. A timing model is developed and measurements are taken to determine the feasibility of the proposal. Theoretical results show that improved routing performance is possible with a combination of hardware and software. Preliminary timing estimates and experiments show that combining the two routing systems could speed up a complex routing problem by a factor of approximation.