• DocumentCode
    1007202
  • Title

    Packaged single-ended CMOS low noise amplifier with 2.3 dB noise figure and 64 dBm IIP2

  • Author

    Li, Z. ; O, K.K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
  • Volume
    40
  • Issue
    12
  • fYear
    2004
  • fDate
    6/10/2004 12:00:00 AM
  • Firstpage
    712
  • Lastpage
    713
  • Abstract
    A single-ended low noise amplifier (LNA) implemented in a foundry 0.18 μm CMOS process is tested on a PC board using the chip-on-board technique. The measured S11 and S22 are less than -10 dB over 5.15-5.35 GHz, which is the lower subband of UNII and HIPERLAN/2 band. The measured noise figure is 2.0 dB and power gain is 15.5 dB at 5.15 GHz, while drawing 5.8 mA of current from a 1.8 V supply. The measured IIP2 is greater than 64 dBm. This extremely high IP2 is due to the tuned response of the LNA. The LNA is suitable for WLAN applications in the lower UNII and HIPERLAN/2 subband.
  • Keywords
    CMOS integrated circuits; MMIC amplifiers; chip-on-board packaging; integrated circuit noise; integrated circuit testing; 0.18 micron; 1.8 V; 15.5 dB; 2 dB; 2.3 dB; 5.15 to 5.35 GHz; 5.8 mA; CMOS low noise amplifier; HIPERLAN/2 subband; LNA; PC board; UNII subband; WLAN applications; chip-on-board technique; integrated circuit noise; noise figure;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20040459
  • Filename
    1305457
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1007202