Self-aligned MESFETs by a dual-level double-lift-off substitutional gate (DDS) technique for high-speed low-power GaAs ICs

Author

Chang, M.F. ; Ryan, Frank J. ; Vahrenkamp, R.P. ; Kirkpatrick, C.G.

Author_Institution

Rockwell International Corporation, Microelectronics Research & Development Center, Thousand Oaks, USA

Volume

21

Issue

8

fYear

1985

Firstpage

354

Lastpage

356

Abstract

A new self-aligned substitutional gate processing technique which involves dual-level resist patterning was developed for 75 mm (3 in)-diameter GaAs MESFETs IC fabrication. The transconductance of 1 Â¿m gate length DDS E-MESFETs reached a maximum value of 280 mS/mm. E/R ring oscillators showed a 22 ps/gate propagation delay and a 34.5 fJ speed-power product. E/D ring oscillators had a 53 ps/gate propagation delay, a 12.5 fJ speed-power product and a power dissipation of 0.24 mW/gate at 300 K.

Keywords

III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated circuit technology; 0.24 mw/gate power dissipation; 1 micron gate length; 12.5 fJ speed-power product; 22 ps/gate propagation delay; 34.5 fJ speed-power product; 53 ps/gate propagation delay; E/D ring oscillators; E/R ring oscillators; GaAs ICs; IC fabrication; MESFETs; double lift-off technique; dual-level resist patterning; high-speed type; low-power operation; self-aligned method; substitutional gate processing technique;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19850250

Filename

4251105