DocumentCode
1012312
Title
Cell Multiprocessor Communication Network: Built for Speed
Author
Kistler, Michael ; Perrone, Michael ; Petrini, Fabrizio
Author_Institution
IBM Austin Res. Lab., TX
Volume
26
Issue
3
fYear
2006
Firstpage
10
Lastpage
23
Abstract
Multicore designs promise various power-performance and area-performance benefits. But inadequate design of the on-chip communication network can deprive applications of these benefits. To illuminate this important point in multicore processor design, the authors analyze the cell processor´s communication network, using a series of benchmarks involving various DMA traffic patterns and synchronization protocols
Keywords
computer architecture; logic design; microprocessor chips; multiprocessing systems; system-on-chip; DMA traffic patterns; area-performance benefits; cell multiprocessor communication network; multicore processor design; on-chip communication network design; power-performance benefits; synchronization protocols; Bandwidth; Buildings; Communication networks; Concurrent computing; Delay; Energy consumption; High performance computing; Multicore processing; Network-on-a-chip; Process design; Cell Broadband Engine processor; multiprocessor communication network;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2006.49
Filename
1650177
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