Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFETs

Author

Lee, Peter M. ; Ko, Ping K. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

11

Issue

1

fYear

1990

Firstpage

39

Lastpage

41

Abstract

The authors report that comparison with measured 75-MHz CMOS ring-oscillator speed degradation suggests that quasi-static circuit aging simulations using DC stress data do not underestimate circuit degradation. Roughly speaking, 10% degradation in NMOSFET linear current results in only about 1.3% increase in CMOS inverter propagation delay. This 10% current degradation occurs in an inverter-based circuit over a time that is about six times the MOSFET DC lifetime at maximum I/sub sub/ and about 30 times the DC lifetime at maximum I/sub sub//sup 3//I/sub ds//sup 2/.<>

Keywords

CMOS integrated circuits; hot carriers; insulated gate field effect transistors; life testing; logic gates; semiconductor device testing; 75 MHz; CMOS inverter propagation delay; CMOS ring-oscillator; DC hot-carrier lifetime; DC stress data; I/sub sub/; I/sub sub//sup 3//I/sub ds//sup 2/; MOSFET DC lifetime; NMOSFET linear current; circuit degradation; inverter-based circuit; quasi-static circuit aging simulations; speed degradation; Circuit testing; Degradation; Hot carriers; Intrusion detection; Inverters; MOSFET circuits; Propagation delay; Stress measurement; Substrates; Time measurement;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.46924

Filename

46924