A VLSI chip set for DPCM coding of HDTV signals

For digital HDTV studio-to-studio transmission at 565 Mb/s the hardware implementation of a differential pulse code modulation (DPCM) coding algorithm with 2-D prediction and a fixed code word length is reported. The data rate is reduced by a factor of about two. Noise shaping improves the picture quality of both luminance and chrominance. Parallel processing, a modified DPCM structure, and pipeline techniques are necessary to fulfil the timing constraints. The DPCM and FIFO circuits, the major components of this codec, are designed with a 1.2-μm double metal CMOS technology. The two DPCM chips, one for luminance and one for chrominance, are successfully tested and work correctly up to 44 and 59 MHz, respectively, while the fall-through FIFO with a maximum storage capacity of 1296 b×8 b attains a clock frequency of over 130 MHz. Due to its completely asynchronous operation this FIFO may be useful for other video applications, but a fall-through time of 400 ns must be taken into account