Record low specific on-resistance for low-voltage trench MOSFETs

A process is shown by which both the specific on-resistance R_ds,on and the gate-drain charge density Q_gd can be reduced. Reduction of R_ds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Q_gd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further R_ds,on reduction. Record values for R_ds,on of 4 mΩ·mm² (at V_gs=10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an R_ds,on of 7 mΩ·mm² (at V_gs=10 V) was obtained by using a more box-shaped p-body profile.