BiCMOS circuit technology for a high-speed SRAM

Author

Douseki, Takakuni ; Ohmori, Yasuo

Author_Institution

NTT LSI Labs., Kanagawa, Japan

Volume

23

Issue

1

fYear

1988

Firstpage

68

Lastpage

73

Abstract

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable.<>

Keywords

emitter-coupled logic; integrated circuit technology; integrated memory circuits; monolithic integrated circuits; random-access storage; 1 W; 64 kbit; 7 ns; BiCMOS circuit technology; ECL-compatible static RAM; ECL-interface circuit; decoder; emitter-follower driver; high-speed SRAM; inverter; large capacity memory IC; low-power operation; memory cell array configuration; multiplexer; optimization method; premain decode configuration; word driver; BiCMOS integrated circuits; Decoding; Delay effects; Driver circuits; Inverters; Multiplexing; Optimization methods; Power dissipation; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.258

Filename

258