DocumentCode
1017181
Title
Memory in the fast lane
Author
Prince, Betty
Author_Institution
Memory Strategies International, USA
Volume
31
Issue
2
fYear
1994
Firstpage
38
Lastpage
41
Abstract
The author describes how the demand for higher-bandwidth memories in systems from multiprocessing to multimedia has designers pulling out all the stops. Topics discussed include: cache hierarchy; rapider RAM; wider data; application specific DRAMs; synchronous memories; and SRAM caches.<>
Keywords
DRAM chips; SRAM chips; buffer storage; multimedia systems; multiprocessing systems; RAM; SRAM caches; application specific DRAMs; cache hierarchy; high-bandwidth memories; multimedia; multiprocessing; synchronous memories; Bandwidth; Circuit testing; Computer architecture; Costs; DRAM chips; Delay; Microprocessors; Plugs; Random access memory; Read-write memory;
fLanguage
English
Journal_Title
Spectrum, IEEE
Publisher
ieee
ISSN
0018-9235
Type
jour
DOI
10.1109/6.259491
Filename
259491
Link To Document