• DocumentCode
    1019321
  • Title

    Pattern matching and refinement hybrid approach to circuit comparison

  • Author

    Pelz, Georg ; Roettcher, Uli

  • Author_Institution
    Dept. of Electr. Eng., Duisburg Univ., Germany
  • Volume
    13
  • Issue
    2
  • fYear
    1994
  • fDate
    2/1/1994 12:00:00 AM
  • Firstpage
    264
  • Lastpage
    276
  • Abstract
    We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits. Typically, a hierarchical schematic has to be compared with a flat netlist extracted from the layout. In our approach, this is accomplished by successive, bottom-up matching of schematic cells in the layout netlist, thus reconstructing the schematic hierarchy. The method is independent of circuit technology and design style. A sophisticated hierarchy handling scheme enables the usage of ill-structured schematic hierarchies. The typical problems in circuit comparison are overcome in a quite natural way by pattern matching. Real-life examples indicate the tool´s suitability in function and performance. The hybrid approach is a mixture between the pattern matching approach and the traditional refinement technique. In this way, the advantages of both methods can be exploited
  • Keywords
    VLSI; circuit layout; network topology; CMOS NAND pattern; VLSI design; arbitrary subcircuits; chip level verification; circuit comparison; flat netlist; hierarchical processing; hierarchical schematic; hierarchy handling scheme; layout netlist; pattern matching; refinement hybrid approach; successive bottom-up matching; topology; Circuit simulation; Circuit synthesis; Hip; Labeling; Logic gates; Manufacturing automation; Microelectronics; Network topology; Pattern matching; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.259949
  • Filename
    259949