0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file

Author

Hara, Hiroyuki ; Sakurai, Takayasu ; Nagamatsu, Tetsu ; Seta, Katsuhiro ; Momose, Hiroshi ; Niitsu, Yoichirou ; Miyakawa, Hiroyuki ; Matsuda, Kouji ; Watanabe, Yoshinori ; Sano, Fumihiko ; Chiba, Akihiko

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1579

Lastpage

1584

Abstract

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip

Keywords

BiCMOS integrated circuits; application specific integrated circuits; buffer storage; integrated logic circuits; integrated memory circuits; 0.1 to 0.6 W; 0.5 micron; 3.3 V; 32 kbyte; ASIC; BiCMOS macros; ECL HIT logic; adder; high-speed operation; low power consumption; low supply voltage; self-aligned threshold inverter; sense amplifier; standard cells; table look-aside buffer; ten-port register file; Adders; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Energy consumption; Low voltage; Operational amplifiers; Pulse inverters; Registers; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165339

Filename

165339