Highly effective junction isolation structures for PICs based on standard CMOS Process

Author

Starke, Thomas K H ; Holland, Paul M. ; Hussain, Shahzad ; Jamal, W.M. ; Mawby, P.A. ; Igic, Petar M.

Author_Institution

Sch. of Eng., Univ. of Wales Swansea, UK

Volume

51

Issue

7

fYear

2004

fDate

7/1/2004 12:00:00 AM

Firstpage

1178

Lastpage

1184

Abstract

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.

Keywords

CMOS logic circuits; isolation technology; logic design; power integrated circuits; substrates; 0.6 micron; CMOS process; CMOS technology; LDMOSFET; junction isolation structures; laterally diffused MOSFET; logic circuitry; multiring active analogic protection; negative feedback-activated junction isolation; power integrated circuits; substrate current blocking; CMOS process; CMOS technology; Dielectric substrates; Integrated circuit technology; Isolation technology; Logic circuits; Logic devices; Power integrated circuits; Protection; Silicon on insulator technology; Junction isolation; LDMOSFET; MAAP; PIC; Power integrated circuit; laterally diffused MOSFET; multi-ring active analogic protection; power ICs;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2004.829895

Filename

1308644