12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit

Author

Chin, Kenneth ; Chuang, Ching-Te ; Warnock, James D.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1648

Lastpage

1650

Abstract

An NTL circuit with a charge-buffered active-pulldown emitter-follower stage is described. The circuit utilizes the diffusion capacitance of a charge-storage diode (CSD) as the coupling element between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor to generate a large dynamic current for the pull-down transistor and to provide a speedup effect on the switching logic stage. Implemented in a 0.8-μm double-poly trench-isolated self-aligned bipolar process, unloaded gate delays of 12.8 ps/1.0 mW, 15.4 ps/0.71 mW, and 18.0 ps/0.53 mW have been achieved

Keywords

bipolar integrated circuits; integrated logic circuits; 0.53 to 1 mW; 0.8 micron; 12.8 to 18 ps; active-pulldown; charge-buffered; charge-storage diode; diffusion capacitance; double-poly; emitter-follower stage; self-aligned bipolar process; switching logic stage; trench-isolated; Buffer storage; Capacitance; Capacitors; Coupling circuits; Delay; Diodes; Energy consumption; Logic circuits; Power supplies; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165347

Filename

165347