Low Power and Power Management for CMOS—An EDA Perspective

Power management and power optimization continue to play a crucial role as CMOS technology scales further beyond 45 nm not just because of the stringent power budgets, particularly for untethered systems, but also because of reliability considerations, and of packaging and cooling costs as well. Process technologists have the biggest role in coming up with device solutions to optimize dynamic power and, most importantly, to suppress wasteful leakage power. However, the management of power hardly stops there. Developers of engineering design automation (EDA) tools have a major and significant role in automating power management techniques realized by circuit, logic, and system designers. This paper addresses power management and optimization with a special emphasis on the role the EDA tools play. It also discusses the close chronological relation between advances in device technology and the corresponding efforts that follow in design automation to address the implications of those device advances.