Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON

The flicker noise in MOSFETs with short gate lengths (L < 1 mum) is severely degraded by the presence of a thick high-k gate dielectric layer. The gate length dependence of flicker noise becomes stronger with increasing high-k dielectric thickness - but only for n-FET. To explain these phenomena, a model based on excess traps at the gate edges has been developed. This model explains the flicker-noise dependence on high-k dielectric thickness and gate length and has successfully reproduced the experimental data. Based on the model, the impact of gate-length scaling is evaluated for future mixed-signal ICs using high-k gate-dielectric technology. The deployment of high-k gate dielectric adds another gate-length-scaling limit for analog devices due to the noise consideration.