Low memory and low complexity VLSI implementation of JPEG2000 codec

Author

Huang, Quanping ; Zhou, Rongzheng ; Hong, Zhiliang

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai, China

Volume

50

Issue

2

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

638

Lastpage

646

Abstract

In this paper, the VLSI implementation of a low memory and low complexity architecture of JPEG2QOO codec is presented. By analyzing the fix-point computation of discrete wavelet transform (DWT), a low memory implementation for lossy JPEG2000 codec is proposed. An efficient memory organization is adopted in this implementation to improve the speed of embedded block coding with optimized truncation (EBCOT) hardware accelerator. A buffered architecture is adopted in lifting based DWT to reduce the hardware cost, to achieve the higher hardware utilization and to reduce complexity of address generator. For EBCOT, a column-based coding of Tier-1 block coding engine and an effectively simplified Tier-2 coding engine are proposed. The proposed architecture of JPEG2000 codec is implemented in test camera chip that has been manufactured in 0.25 um CMOS digital process.

Keywords

CMOS digital integrated circuits; VLSI; block codes; codecs; discrete wavelet transforms; image coding; 0.25 mum; CMOS digital process; EBCOT; JPEG2QOO codec; Tier-1 block coding engine; Tier-2 coding engine; VLSI implementation; address generator; buffered architecture; camera chip; discrete wavelet transform; embedded block coding with optimized truncation; hardware accelerator; hardware utilization; low complexity architecture; low memory architecture; memory organization; very large scale integration; Block codes; Codecs; Computer architecture; Costs; Discrete wavelet transforms; Engines; Hardware; Testing; Very large scale integration; Wavelet analysis;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2004.1309443

Filename

1309443