High-speed unit-cell for Josephson LSI circuits using Nb/AlOx/Nb junctions

In this paper, we will discuss the design, fabrication and evaluation of an OR gate and a unit-cell for Josephson logic LSI circuits using all niobium junctions. We fabricated the unit-cell using two Modified Variable Threshold Logic (MVTL) OR gates and one single-junction AND gate. The cell performs the logical opration (A+B).(C+D), which is the basic operation of the dual rail logic method, suitable for Josephson devices. The gates utilized Nb/AlOx/Nb Josephson junctions with a minimum diameter of 2.5 μm, Nb wirings, Mo resistors, and SiO2insulators. The cell size, complete with supply resistors, was 82 μm × 132 μm. The gate delays were measured using the Josephson sampling technique with two sampling heads. The minimum delay of the OR gate in the cell was 4.2 ps, and that of the three-fanout cell was 11.5 ps. The experimental results were consistent with calculations based on measured parameters.