The method of estimating delay in switching circuits and the figure of merit of a switching transistor

A simple method of estimating delay in a switching network is outlined. The simplicity of formulas thus obtained makes them readily applicable for circuit comparisons or device optimization purposes. It is shown that a term involving the product of base resistance and diffusion capacitance forms a major limitation on high-speed, voltage-driven circuits. This method is applicable to a general class of switching problems.