A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

Author

Sone, Kazuya ; Nishida, Yoshio ; Nakadai, Naotoshi

Author_Institution

Microelectron. Res. Labs., NEC Corp., Sagamihara, Japan

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1180

Lastpage

1186

Abstract

A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply

Keywords

BiCMOS integrated circuits; adders; analogue-digital conversion; error correction; pipeline processing; 0.8 mum; 100-Msample/s; 335 MHz; 335-MHz unity-gain frequency op amp; 94 dB; 950 mW; BiCMOS ADC; DC open-loop gain; carry-look-ahead adder; current-switching sampling gates; digital error correction; pipelined subranging analog-digital converter; power dissipation; track-and-hold amplifier; Adders; BiCMOS integrated circuits; Clocks; Error correction; Frequency; Operational amplifiers; Power dissipation; Power supplies; Sampling methods; Tracking loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.261990

Filename

261990