DocumentCode
1027421
Title
Bifurcations in iterative decoding and root locus plots
Author
Kellett, Christopher M. ; Weller, Steven R.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Univ. of Newcastle, Callaghan, NSW
Volume
2
Issue
12
fYear
2008
fDate
12/1/2008 12:00:00 AM
Firstpage
1086
Lastpage
1093
Abstract
A class of error correction codes called dasialow-density parity-check (LDPC)dasia codes have been the subject of a great deal of recent study in the coding community as a result of their ability to approach Shannondasias fundamental capacity limit. Crucial to the performance of these codes is the use of an dasiaiterativedasia decoder. These iterative decoders are effectively high-dimensional, nonlinear dynamical systems and, consequently, control-theoretic tools are useful in analysing such decoders. The authors describe LDPC codes and the decoding algorithm and make a connection between the fixed points of the decoding algorithm and the well-known root locus plot. Through two examples of LDPC codes, the authors show that the root locus plot visually captures the bifurcation behaviour of iterative decoding that occurs at the signal-to-noise ratio predicted by Shannondasias noisy channel coding theorem.
Keywords
bifurcation; iterative decoding; parity check codes; root loci; ´low-density parity-check codes; bifurcations; error correction codes; iterative decoding; noisy channel coding theorem; nonlinear dynamical systems; root locus plots; signal-to-noise ratio;
fLanguage
English
Journal_Title
Control Theory & Applications, IET
Publisher
iet
ISSN
1751-8644
Type
jour
DOI
10.1049/iet-cta:20080090
Filename
4708685
Link To Document