Driving the LHCb front-end readout

The timing and fast control (TFC) system is responsible for controlling and distributing timing, trigger and synchronous commands to the LHCb front-end (FE) electronics. It is different from the equivalent systems of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, the TFC mastership of a configurable ensemble of FE electronics is centralized in one module: the Readout Supervisor. A pool of optional Readout Supervisors allows mastering of all or separate combinations of subsystems in parallel by remote programming of a patch panel in the distribution network. The speed requirements and the multifunctionality of the Readout Supervisor necessitate optimal technological solutions. At the same time the logic must be modifiable to support extensions or changes in the running modes. A first prototype has been built using field-programmable gate arrays (FPGAs) for the entire logic and it has been tested successfully. This paper gives an overview of the system architecture and describes in more detail the functions and the implementation of the Readout Supervisor.