• DocumentCode
    1030968
  • Title

    Serial-data computation on twin pipelines

  • Author

    McGregor, M.S. ; Smith, S.G. ; Denyer, P.B. ; Murray, A.F.

  • Author_Institution
    University of Edinburgh, Department of Electrical Engineering, Edinburgh, UK
  • Volume
    23
  • Issue
    6
  • fYear
    1987
  • Firstpage
    292
  • Lastpage
    293
  • Abstract
    The letter describes a novel two-wire data representation for bit-serial architectures. The technique offers twice the data throughput of conventional bit-serial systems at a cost of much less than twice the hardware. In some cases less hardware than the conventional one-wire representation can be used to implement the two-wire representation.
  • Keywords
    VLSI; computer architecture; logic design; bit-serial architectures; serial data computation; twice data throughput; twin pipelines; two-wire data representation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19870212
  • Filename
    4257539
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1030968