A VLSI motion estimator for video image compression

Author

Wu, Chen-Mie ; Yeh, Ding-Kuen

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

39

Issue

4

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

837

Lastpage

846

Abstract

The authors present a VLSI motion estimator based on the full-search block-matching algorithm (FSBMA) for video image compression. To improve the performance, a novel two-dimensional SIMD-systolic architecture has been derived. Currently, based on a 0.8 μm CMOS technology, a VLSI chip has been implemented and fabricated for such an architecture. The chip is functionally correct and packaged as a 68-pin PGA chip. With such a chip, the motion vector of each 16×16 block can be generated in 1252 cycles (i.e., 54.4 μs for 23 MHz systems). Therefore, even with a small pin-count, a high-performance FSBMA-based motion estimator can still be developed

Keywords

CMOS integrated circuits; VLSI; data compression; image coding; logic arrays; motion estimation; systolic arrays; video signals; 0.8 micron; 23 MHz; 2D SIMD-systolic architecture; CMOS technology; PGA chip; VLSI motion estimator; full-search block-matching algorithm; motion vector; video image compression; CMOS technology; Computer architecture; Current measurement; Electronics packaging; Hardware; Image coding; Motion estimation; Tracking; Very large scale integration; Video compression;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.267407

Filename

267407