Designing the TFP microprocessor

Author

Hsu, Peter Yan-Tek

Author_Institution

Silicon Graphics Comput. Syst., Mountain View, CA, USA

Volume

14

Issue

2

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

23

Lastpage

33

Abstract

Designed to efficiently support large, real-world, floating-point-intensive applications, the TFP (short for Tremendous Floating-Point) microprocessor is a superscalar implementation of the Mips Technologies architecture. This floating-point, computation-oriented processor uses a superscalar machine organization that dispatches up to four instructions each clock cycle to two floating-point execution units, two memory load/store units, and two integer execution units. Its split-level cache structure reduces cache misses by directing integer data references to a 16-Kbyte on-chip cache, while channeling floating-point data references off chip to a 4 Mbyte cache.<>

Keywords

digital arithmetic; microprocessor chips; 16 kByte; 16-Kbyte on-chip cache; 4 MByte; Mips Technologies architecture; TFP microprocessor; Tremendous Floating-Point microprocessor; computation-oriented processor; floating-point data references; floating-point-intensive applications; integer data references; integer execution units; memory load/store units; split-level cache structure; superscalar implementation; Bandwidth; Clocks; Computer aided instruction; Computer architecture; Costs; Delay; Microprocessors; Network servers; Supercomputers; Workstations;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.272835

Filename

272835