An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

Author

Oklobdzija, Vojin G.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

2

Issue

1

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

124

Lastpage

128

Abstract

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both: logic synthesis and an algorithmic approach. The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 0.6 /spl mu/m CMOS technology. The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed.<>

Keywords

CMOS integrated circuits; bipolar integrated circuits; circuit layout CAD; detector circuits; integrated logic circuits; logic CAD; 0.6 micron; 200 ps; CMOS technology; ECL technology; LZD circuit; algorithmic design; leading zero detector circuit; logic synthesis; modular scalable circuit; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit synthesis; Detectors; Logic circuits; Logic design; Minimization methods; Registers;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.273153

Filename

273153