A 50-MHz CMOS geometrical mapping processor

Author

Yoshimura, Hiroshi ; Nakanishi, Tadashi ; Yamauchi, Hironori

Author_Institution

NTT Human Interface Lab., Kanagawa, Japan

Volume

36

Issue

10

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1360

Lastpage

1364

Abstract

A recently developed microprogrammable, high-resolution, real-time geometrical mapping processor VLSI is presented. The processor computes pixel addresses within the frame-buffer memory according to user-specified geometrical mapping functions. Its architecture permits high-speed operations and library extensions through a combination of elementary functions. It includes a CORDIC function generator, consisting of a one-dimensional pipeline array with high-speed parallel arithmetic circuits, and a pipeline control method. This results in a 50-MHz throughput rate with an accuracy of 20 bits using 1.2-μm CMOS technology. The processor will be useful in high-definition television (HDTV) systems

Keywords

CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; high definition television; parallel architectures; pipeline processing; real-time systems; telecommunications computing; television equipment; 1.2 micron; 50 MHz; CMOS technology; CORDIC function generator; DSP chip; HDTV; VLSI; architecture; frame-buffer memory; geometrical mapping processor; high-definition television; high-resolution; high-speed operations; library extensions; microprogrammable; one-dimensional pipeline array; parallel arithmetic circuits; pipeline control method; real-time; user-specified geometrical mapping functions; Arithmetic; CMOS process; CMOS technology; Circuits; Computer architecture; HDTV; Libraries; Pipelines; Signal generators; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.44351

Filename

44351