Converting a bulk radiation-hardened BiCMOS technology into a dielectrically-isolated process

A radiation-hardened dielectrically isolated BiCMOS process has been developed by retrofitting dielectric isolation to an existing radiation-hardened JI (junction-isolated) process. The process is fabricated on a bonded-wafer silicon-on-insulator (SOI) substrate and employs deep trenches for lateral device isolation. The isolation technique employed is similar to that used on advanced commercial complementary-bipolar processes. Trench/substrate induced defects are sensitive to the device layout and process flow. Optimization of the trench and posttrench processing and the device layouts has reduced the defect densities to acceptable levels. The defect density levels obtained are consistent with the economic manufacture of VLSI circuits. The dose-rate performance of the process has been improved without compromising the total-dose hardness