Multiprocessor performability analysis

Author

Lopez-Benitez, Noe ; Trivedi, Kishor S.

Author_Institution

Dept. of Comput. Sci., Texas Tech. Univ., Lubbock, TX, USA

Volume

42

Issue

4

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

579

Lastpage

587

Abstract

Performability models of multiprocessor systems and their evaluation are presented. Two cases in which hierarchical modeling is applied are examined. Modified stochastic Petri net (MSPN)-based fault models of processor arrays, and a fault handling model to account for near coincident, permanent, transient, and intermittent faults are discussed. Performability results based on capacity-based reward assignments are reported. A simple MSPN-based model for multiprocessor systems, is introduced, and a closed queuing network to derive performance rewards is discussed. Several multiprocessor configurations are compared

Keywords

Petri nets; fault tolerant computing; multiprocessing systems; performance evaluation; stochastic processes; capacity-based reward assignments; closed queuing network; fault handling model; hierarchical modeling; intermittent faults; modified stochastic Petri net fault models; multiprocessor performability analysis; multiprocessor systems; near coincident faults; permanent faults; processor arrays; transient faults; Degradation; Fault detection; Fault tolerant systems; Fires; Multiprocessing systems; Performance analysis; Performance evaluation; Predictive models; Stochastic systems; Switches;

fLanguage

English

Journal_Title

Reliability, IEEE Transactions on

Publisher

ieee

ISSN

0018-9529

Type

jour

DOI

10.1109/24.273586

Filename

273586