A new compact dual-core architecture for AES encryption and decryption

Author

Hua Li ; Jianzhou Li

Author_Institution

Dept. of Math. & Comput. Sci., Univ. of Lethbridge, Lethbridge, AB

Volume

33

Issue

42433

fYear

2008

Firstpage

209

Lastpage

213

Abstract

This article presents a new compact architecture, consisting of two independent cores that process encryption and decryption simultaneously, for the Advanced Encryption Standard (AES) algorithm. The corresponding new compact key generation unit with 32-bit datapath is also explored to provide round keys on the fly for encryption and decryption. A novel way to implement ShiftRows/InvShiftRows, one of the key designs in the compact 32-bit architecture, is proposed. The new AES implementation requires only 16 629 gate equivalents on the 0.35 mum CMOS technology from CSMC Technologies Corporation, while providing encryption and decryption in parallel with 335 Mbits/s throughput.

Keywords

CMOS integrated circuits; cryptography; microprocessor chips; Advanced Encryption Standard; CMOS technology; ShiftRows/InvShiftRows; bit rate 335 Mbit/s; compact key generation unit; dual-core architecture; size 0.35 mum; Application specific integrated circuits; CMOS technology; Communication system security; Cryptography; Field programmable gate arrays; Hardware design languages; Matrices; NIST; Standards development; Throughput; AES; ASIC; compact architecture; dual cores;

fLanguage

English

Journal_Title

Electrical and Computer Engineering, Canadian Journal of

Publisher

ieee

ISSN

0840-8688

Type

jour

DOI

10.1109/CJECE.2008.4721627

Filename

4721627