• DocumentCode
    1045327
  • Title

    Design Implications of Single Event Transients in a Commercial 45 nm SOI Device Technology

  • Author

    Kleinosowski, AJ ; Cannon, Ethan H. ; Pellish, Jonathan A. ; Oldiges, Phil ; Wissel, Larry

  • Author_Institution
    Boeing Co., Seattle, WA
  • Volume
    55
  • Issue
    6
  • fYear
    2008
  • Firstpage
    3461
  • Lastpage
    3466
  • Abstract
    This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets.
  • Keywords
    semiconductor device measurement; semiconductor device models; silicon-on-insulator; transient analysis; SOI device technology; circuit structures; clock circuits; pass gates; single event transient; size 45 nm; Circuits; Clocks; Flip-flops; Inorganic materials; Logic; Paper technology; Protection; Semiconductor materials; Silicon; Single event upset; Modeling; radiation event; single event transient (SET); single event upset (SEU); soft error;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2008.2005191
  • Filename
    4723723
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1045327